1. Field of the Invention
The present invention relates to an analog-to-digital (AD) converter applicable to a solid-state image pickup device represented by, for example, a complementary metal-oxide-semiconductor (CMOS) image sensor, a solid-state image pickup device including the AD converter, and a camera system.
2. Description of the Related Art
In recent years, CMOS image sensors have been drawing attention as solid-state image pickup devices (image sensors), in place of charge-coupled device (CCD) image sensors.
This is because CMOS image sensors overcome the problems of CCD image sensors, including that a dedicated manufacturing process is necessary for fabricating CCD pixels, a plurality of power supply voltages are necessary for the operation of a CCD image sensor, and a system including the CCD image sensor becomes very complicated due to the necessity of operating a plurality of peripheral integrated circuits (ICs) in a combined manner.
CMOS image sensors can be manufactured using a process similar to the process of manufacturing general CMOS ICs. Also, a CMOS image sensor can be driven by a single power supply. Furthermore, an analog circuit and a logic circuit using CMOS processes can be mixed in a single chip, resulting in a reduction of the number of peripheral ICs. That is, CMOS sensors have great advantages.
An output circuit of a CCD image sensor is generally a 1-channel (ch) output using a floating diffusion (FD) amplifier with an FD.
In contrast, a CMOS image sensor has an FD amplifier in each pixel and generally uses a column-parallel output scheme that selects a row from an array of pixels and simultaneously outputs signals read from the selected row of pixels in a column direction.
Because it is difficult to obtain sufficient drive power using the FD amplifiers arranged in the pixels, the date rate is necessary to be dropped. In this regard, parallel processing is considered to be advantageous.
A general CMOS image sensor will now be described below.
FIG. 1 shows an example of a pixel in a CMOS image sensor, the pixel including four transistors.
A pixel 10 includes, for example, a photodiode 11 serving as a photoelectric transducer. The pixel 10 has four transistors for the photodiode 11, namely, a transfer transistor 12, an amplifying transistor 13, a selecting transistor 14, and a reset transistor 15, which serve as active elements.
The photodiode 11 converts incident light into electric charge (electrons in this example) whose amount is in accordance with the quantity of the incident light.
The transfer transistor 12 is connected between the photodiode 11 and an FD. By supplying a drive signal to a gate (transfer gate) of the transfer transistor 12 through a transfer control line LTx, the electrons obtained by photoelectric conversion using the photodiode 11 are transferred to the FD.
A gate of the amplifying transistor 13 is connected to the FD. The amplifying transistor 13 is connected to a signal line LSGN via the selecting transistor 14 and, together with a constant current source 16 provided outside the pixel 10, constitutes a source follower.
An address signal is supplied to a gate of the selecting transistor 14 through a selection control line LSEL. When the selecting transistor 14 is turned ON, the amplifying transistor 13 amplifies the potential of the FD and outputs a voltage in accordance with the potential to the output (vertical) signal line LSGN. A signal voltage output from the pixel 10 is output through the signal line LSGN to a pixel-signal reading circuit.
The reset transistor 15 is connected between a power supply line LVDD and the FD. By supplying a reset signal to a gate of the reset transistor 15 through a reset control line LRST, the reset transistor 15 resets the potential of the FD to the potential of the power supply line LVDD.
More specifically, when resetting the pixel 10, the transfer transistor 12 is turned ON, thus discharging the electric charge accumulated in the photodiode 11. Next, the transfer transistor 12 is turned OFF, and the photodiode 11 converts an optical signal into electric charge, and accumulates the electric charge.
At the time of reading, the reset transistor 15 is turned ON, thus resetting the FD. Then, the reset transistor 15 is turned OFF, and the voltage of the FD at that point is output via the amplifying transistor 13 and the selecting transistor 14. This output serves as a P-phase output.
Next, the transfer transistor 12 is turned ON, thus transferring the electric charge accumulated in the photodiode 11 to the FD. The voltage of the FD at that point is output via the amplifying transistor 13. This output serves as a D-phase output.
A difference between the D-phase output and the P-phase output serves as an image signal. Accordingly, not only variations in direct current (DC) components of outputs of the pixels, but also FD reset noise can be removed from the image signal.
These operations are performed at the same time for all pixels included in one row since, for example, the gates of the transfer transistor 12, the selecting transistor 14, and the reset transistor 15 are interconnected on a row-by-row basis.
Various types of pixel-signal reading (output) circuits in column-parallel-output CMOS image sensors have been proposed. One of the most advanced types is the type that includes an analog-to-digital converter (hereinafter abbreviated as “ADC”) in each column, and that obtains a pixel signal as a digital signal.
CMOS image sensors with such column-parallel ADCs are disclosed in, for example, W. Yang, et al., “An Integrated 800×600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304-305, February 1999, and in Japanese Unexamined Patent Application Publication Nos. 2005-278135 and 2005-311933.
FIG. 2 is a block diagram showing an exemplary structure of a solid-state image pickup device (CMOS image sensor) with column-parallel ADCs.
A solid-state image pickup device 20 includes, as shown in FIG. 2, a pixel section 21 serving as an image pickup section, a vertical scanning circuit 22, a horizontal transfer/scanning circuit 23, a timing control circuit 24, an ADC group 25, a digital-to-analog converter (hereinafter abbreviated as “DAC”) 26, an amplifier (sample/hold (S/H)) circuit 27, and a signal processing circuit 28.
The pixel section 21 includes pixels arranged in a matrix. Each pixel includes a photodiode and a built-in amplifier, for example, as shown in FIG. 1.
In the solid-state image pickup device 20, the timing control circuit 24 for generating an internal clock signal, the vertical scanning circuit 22 for controlling row addresses and row scanning, and the horizontal transfer/scanning circuit 23 for controlling column addresses and column scanning are arranged as control circuits for sequentially reading signals from the pixel section 21.
The ADC group 25 includes a plurality of columns of ADCs. Each ADC includes a comparator 25-1 that compares a reference voltage Vslop, which has a ramp waveform obtained by changing a reference voltage generated by the DAC 26 to be a stepped voltage, with a corresponding one of analog signals obtained from pixels in each row through respective vertical signal lines; a counter 25-2 that counts a comparison time; and a latch 25-3 that holds the count result.
The ADC group 25 includes column-parallel ADC blocks, each ADC block having an n-bit digital signal converting function. The ADC blocks are arranged in correspondence with respective vertical signal lines (column lines).
An output of each latch 25-3 is connected to, for example, a 2n-bit-width horizontal transfer line 29.
In correspondence with the horizontal transfer line 29, 2n amplifier circuits 27 and signal processing circuits 28 are arranged (only one amplifier circuit 27 and one signal processing circuit 28 are shown in FIG. 2).
In the ADC group 25, each of the comparators 25-1, which are arranged in respective columns, compares an analog signal read to a corresponding vertical signal line with the reference voltage Vslop (slope waveform that has a certain slope and changes linearly).
On this occasion, the counters 25-2, which are arranged in respective columns, as with the comparators 25-1, are operating. When the potential Vslop having the ramp waveform and a counter value change with a one-to-one correspondence, a potential of the vertical signal line (analog signal) Vsl is converted into a digital signal.
A change in the reference voltage Vslop is for converting a change in voltage into a change in time. By counting that time using a certain cycle (clock), the voltage can be converted into a digital value.
When the analog electric signal Vsl intersects the reference voltage Vslop, the output of the comparator 25-1 is inverted. Inputting of a clock signal to the counter 25-2 is terminated, and accordingly, AD conversion is completed.
After the above-described AD conversion period, the horizontal transfer/scanning circuit 23 inputs data held in the latch 25-3 via the horizontal transfer line 29 and the amplifier circuit 27 to the signal processing circuit 28, thereby generating a two-dimensional image.
In this manner, column-parallel output processing is performed.
Japanese Unexamined Patent Application Publication No. 59-115621 discloses a logic circuit that enables a counter circuit to perform a shift register operation using flip flops FF.